| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To vary a write verification range according to relief of a bit line, a use of a memory array, etc. in a nonvolatile memory where a result of write verification can be aggregated to be a small number of bits to be output. <P>SOLUTION: The nonvolatile memory has a memory array (11) provided with two or more nonvolatile memory cells (MC) connected to two or more bit lines BL, two or more one-bit judgment circuits (31) which compares and judges read data of a verification read unit read from the memory array in write verification operation with write data bits of a corresponding write data latch (29) in parallel by bit correspondence, and a judgement aggregation circuit (32) which aggregates judged results of the two or more one-bit judgment circuits. The judgement aggregation circuit can select bits to be aggregated among the judged results of the two or more one-bit judgment circuits. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
