| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a design method for a synchronous circuit for reducing a peak value of EMI noise by verifying where and how many skews are given and by diversifying the timing of current of power dissipation on the time axis. <P>SOLUTION: The design method for synchronous circuit comprises a first step for implementing a primary layout and wiring of the synchronous circuit using an automatic layout wiring tool by inputting the predetermined condition including a network list, a second step for analyzing a skew as a difference of arriving times of the clock up to each terminal path from the clock source in accordance with a clock tree of the arranged and wired synchronous circuit, a third step for dividing into a plurality of modules I, II, III and IV where the analyzed skew has margin for setup/hold time, a fourth step for additionally inserting a clock skew setting circuit 10 to at least one of the plurality of divided modules I, II, III and IV, and a fifth step for implementing a secondary layout and wiring by adding the clock skew setting circuit 10. <P>COPYRIGHT: (C)2008,JPO&INPIT |
