发明名称 WIRING STRUCTURE AND WIRING FORMING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a wiring structure and wiring forming method of semiconductor integrated circuit of lower resistance with maintaining barrier properties of Cu diffusion prevention function. SOLUTION: A contact region of a diffusion layer 13 is formed under an interlayer insulator film 12 in a substrate 11. An opening 14 for exposure of this diffusion layer 13 and a wiring groove 15 are formed and wiring materials are embedded mainly by a Cu wiring member 16. In the figures, a barrier metal layer BMTL contacting with at least the contact region of the diffusion layer 13 under the interlayer insulator film 12 is formed. Various materials such as Ti/TiN laminate, TaN, or WN can be used for the barrier metal layer BMTL. A thin film 161 containing Al is also formed between the Cu wiring member 16 and the barrier metal layer BMTL. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2008010896(A) 申请公布日期 2008.01.17
申请号 JP20070253524 申请日期 2007.09.28
申请人 SEIKO EPSON CORP 发明人 MASUDA KAZUHIRO
分类号 H01L21/3205;H01L21/28;H01L21/768;H01L23/52 主分类号 H01L21/3205
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