| 摘要 |
The present invention provides a latch circuit that is operable to generate a pulse from first and second clock signals to allow gates in a datapath to propagate data with minimal latency. The first clock signal is a version of the system clock and the second control signal is a time-shifted, inverted version of the system clock signal. Each of the individual latches in a datapath comprises data propagation logic. In one embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an "implicit" pulse. In another embodiment of the invention, the data propagation logic uses the first and second clock signals to generate an "explicit" pulse. The implicit and explicit pulses are used to control the transmission gate of the latch to provide propagation of data through the latch with minimal latency.
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