发明名称 Multi-Level Memory Architecture With Data Prioritization
摘要 In a method of controlling computer-readable memory that includes a plurality of memory locations, a usage frequency of a data unit stored in a first memory location is determined. The data unit is moved to a second memory location, different from the first memory location that is selected based on a correspondence between a known latency of the second memory location and the usage frequency of the data unit, in which the second memory location is the primary data storage location for the data unit.
申请公布号 US2008016297(A1) 申请公布日期 2008.01.17
申请号 US20060457234 申请日期 2006.07.13
申请人 BARTLEY GERALD K;BORKENHAGEN JOHN M;GERMANN PHILIP R;HOVIS WILLIAM P 发明人 BARTLEY GERALD K.;BORKENHAGEN JOHN M.;GERMANN PHILIP R.;HOVIS WILLIAM P.
分类号 G06F13/00 主分类号 G06F13/00
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