| 摘要 |
PROBLEM TO BE SOLVED: To provide a hardware accelerator which performs mode transition at high speed. SOLUTION: In this information processor having a byte code accelerator BCA which converts an intermediate language (byte code) of stack base into an instruction of a register base, the BCA and a selector SEL for switching instructions are arranged between an instruction fetching part FET and a decoding part DEC and data transfer paths (P4, P5) are provided between the BCA and a register file REG_FILE. When the byte code accelerator BCA is started, a P3 side of a converted CPU instruction is selected by the selector SEL and supplied to the decoding part DEC. When the intermediate language can not be converted by the BCA, a mode transits in order to perform software processing. During processing for performing mode transition, mode switching is allowed at high speed by performing transfer of internal information of the BCA in parallel between the BCA and the REG_FILE by using the data transfer paths (P4 and P5). COPYRIGHT: (C)2008,JPO&INPIT
|
