| 摘要 |
A loopback module is disclosed in which N differential High Speed Serial (HSS) digital data input channels are received and sent to a serial to parallel converter, whose output is M-bit wide parallel data. By doing so, the effective data rate is divided down by M to 1/M "fabric" speeds. If the channels contain an embedded clock, the clock is extracted. The parallel data is then sent to a non-blocking crossbar switch, which is able to route any of the N M-bit parallel data inputs to any of Q parallel data outputs by effectively utilizing one multiplexer for each parallel output. Each parallel data output of the crossbar is sent to a parallel to serial converter, whose output is a high speed serial output. Each high speed serial output is fed into a jitter generator circuit, and then to an output driver.
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