发明名称 |
LATENCY OPTIMIZED RESYNCHRONIZATION SOLUTION FOR DDR/DDR2 SDRAM READ PATH |
摘要 |
An apparatus for synchronizing memory data signals is provided. The apparatus comprises a first interface circuit (110) that is configured to generate a differential clock signal in a strobe domain and to convey a data signal to a data bus (110), a second interface circuit (120) in a clock domain that is configured to receive the data signal (170) from the data bus and a synchronization circuit that is configured to adjust the data signal (170) between the strobe domain and the clock domain such that integrity of information encoded by the data signal is preserved. Methods of using the apparatus are also disclosed. |
申请公布号 |
WO2007125519(A3) |
申请公布日期 |
2008.01.10 |
申请号 |
WO2007IB51617 |
申请日期 |
2007.05.02 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V.;VINK, JAN |
发明人 |
VINK, JAN |
分类号 |
G11C7/10;G11C7/22;G11C11/4076;G11C11/4093;G11C11/4096 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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