| 摘要 |
A display substrate and a display panel having the same are provided to reduce the size of a parasitic capacitor formed in a gate line by forming an opening in a shielding electrode and a common electrode corresponding to the gate line, thereby reducing the delay of a gate signal by increasing the width of the gate line without an increase of the parasitic capacitor. A display substrate comprises a base substrate, a gate line(GL), a data line, a pixel electrode(PE), and a shielding electrode(SC). Unit pixel areas disposed in a matrix form are defined on the base substrate. The gate line is extended between the unit pixel areas. The data line crosses the gate line and is extended between the unit pixel areas. The pixel electrode is disposed within the unit pixel areas and is electrically connected to the output electrode of a switching device electrically connected to the gate line and the data line. The shielding electrode is formed in the upper part of the gate line and the data line and has openings(OP1,OP2) for exposing part of the gate line.
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