| 摘要 |
A single chip dynamic random access memory has a memory core, including dynamic random access memory cells, and a clock receiver circuit to receive an external clock signal. A delay locked loop circuit is coupled to the clock receiver circuit. In a first power mode, the delay locked loop circuit and the clock receiver circuit are turned on. Power consumption in the first power mode is less than that consumed while in an active mode. In a second power mode, the delay locked loop circuit is turned off. The memory is configured to receive a command that specifies a power down mode, to turn off the delay locked loop circuit in response to the command that specifies the power down mode, and to operate the memory device in a standby power mode. The delay locked loop circuit and the clock receiver circuit are turned on in a standby mode.
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