| 摘要 |
Methods and apparatus to manage cache coherency are disclosed. In one embodiment, an apparatus comprises a first processor comprising a first processing unit, a first cache memory, and a first coherence controller, and an input/output module having one or more output ports. The first coherence controller comprises an arbitration logic module to direct a message into a processing pipeline and an output issue logic module. The output issue logic module analyzes a message in the processing pipeline, directs the message to an output queue when an output port is unavailable or when the message cannot bypass the output queue, and sends the message to the output port when one or more output ports are available or when the output queue can be bypassed.
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