发明名称 Dynamic configuration of processor core banks
摘要 A method may comprise determining a first reliability rank associated with a first processor core, determining a second reliability rank associated with a second processor core, and associating the first processor core and the second processor core with a first processor core bank. The association of the first processor core and the second processor core is based on the first reliability rank and the second reliability rank.
申请公布号 US2008005538(A1) 申请公布日期 2008.01.03
申请号 US20060479573 申请日期 2006.06.30
申请人 APPARAO PADMASHREE K;VELHAL RAVINDRA V 发明人 APPARAO PADMASHREE K.;VELHAL RAVINDRA V.
分类号 G06F15/00 主分类号 G06F15/00
代理机构 代理人
主权项
地址