Secure output circuit with a single channel periphery connection for the output of a bus participant

摘要

The circuit has a single-channel periphery connection (PA) for connecting a load and designed as a terminal. Two output drivers e.g. FET, (101, 102) are connected in series between a supply voltage (Uv) and the periphery connection. Each driver is connected with a logic through separated control channels (OUT-LK1, OUT-LK2) for controlling the drivers, where the logic is assigned to an output module. A suppressor diode (103) is provided downstream to the drivers and is connected parallel to the periphery connection. An independent claim is also included for a method for testing an output circuit.