SILICON-ON-INSULATOR (SOI) MEMORY DEVICE

摘要

A single-poly SOI memory cell includes a PMOS select transistor serially connected with a floating-gate PMOS transistor on an SOI substrate. The PMOS select transistor includes a select gate, a P⁺ source region and a P⁺ drain/source region. The floating-gate PMOS transistor includes a floating gate, a P⁺ drain region and the P⁺ drain/source region, wherein the P⁺ drain/source region is shared by the PMOS select transistor and the floating-gate PMOS transistor. A floating first N⁺ doping region is disposed within the P⁺ drain/source region. The first N⁺ doping region, which is adjacent to the floating gate, acts as a source-tie pick-up.