| 摘要 |
The RF power amplifier includes first and second amplifiers Q 1 and Q 2 as final-stage amplification power devices connected in parallel between an input terminal RF_In and an output terminal RF_Out. The amplifiers Q 1 and Q 2 are formed on one semiconductor chip. The first bias voltage Vg 1 of the amplifier Q 1 is set to be higher than the second bias voltage Vg 2 of the amplifier Q 2 so that the amplifier Q 1 is operational between Class B and AB, and Q 2 is operational in Class C. The first effective device size Wgq 1 of the amplifier Q 1 is intentionally set to be smaller than the second effective device size Wgq 2 of the amplifier Q 2 beyond a range of a manufacturing error of the semiconductor chip. An RF power amplifier that exhibits a high power-added efficiency characteristic regardless of whether the output power is High or Low can be materialized.
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