发明名称 |
Kontrolle der Ausführung eines Algorithmuses durch eine integrierte Schaltung |
摘要 |
The process involves starting an execution of a calculation, and starting another execution of the same calculation once the former execution has freed a block and its process in a second. The executions are synchronized such that the latter execution uses a hardware block only when the former execution passes to the next block. The identity between the two results is verified at the end of execution of both the calculations. - An INDEPENDENT CLAIM is also included for a chip card. |
申请公布号 |
DE602005003258(D1) |
申请公布日期 |
2007.12.27 |
申请号 |
DE20056003258T |
申请日期 |
2005.04.22 |
申请人 |
ST MICROELECTRONICS S.A. |
发明人 |
LLARDET, PIERRE-YVAN;TEGLIA, YANNICK |
分类号 |
G06F21/02;G06F21/00 |
主分类号 |
G06F21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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