发明名称 ROW BLOCK SELECTION CIRCUIT AND METHOD FOR ALLOCATING ROW REDUNDANCY DELAY TIME IN MEMORY DEVICE
摘要 A row block selection circuit and a method for allocating row redundancy delay time are provided to increase t_RCD(Ras to Cas Delay time) by removing unnecessary row redundancy delay time. According to a row selection circuit for transmitting a block selection signal to a row decoder, a number of block signal generation parts(552,554,556,558) receive a pre-decoded address signal(DRAij) and output a block selection signal. A compensation cell driving part(560) receives the pre-decoded address signal, and outputs the block selection signal and a compensation command signal to the row decoder and the block signal generation part respectively, when the selected cell block does not operate normally. A delay circuit(510,520,530,540) delays the block selection pulse signal, and outputs a block selection signal by performing logic AND operation of the delayed block selection pulse signal and the compensation command signal. The delay circuit delays the block selection pulse signal for a constant time in proportion to signal movement time between the compensation cell driving part and the block signal generation part of the selected cell block.
申请公布号 KR20070120753(A) 申请公布日期 2007.12.26
申请号 KR20060055413 申请日期 2006.06.20
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHOO, CHUL HWAN;LEE, DONG SU
分类号 G11C8/12;G11C8/10 主分类号 G11C8/12
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