| 摘要 |
The present invention relates to a processor that, as its main feature, has an internal raster of ALUs, with the help of which sequential programs are executed. The connections between the ALUs are automatically created at runtime dynamically by means of multiplexers. A central decoding and configuration unit that creates configuration data for the ALU grid from a stream of conventional assembler commands at runtime is responsible for creating the connections. In addition to the ALU grid, a special unit for the execution of memory accesses and another unit for the processing of branch instructions are provided. The novel architecture that is the foundation of the processor makes efficient execution of both control flow- and data flow-oriented tasks possible. |
