发明名称 |
INTERLOCKED SYNCHRONOUS PIPELINE CLOCK GATING |
摘要 |
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
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申请公布号 |
US2007294548(A1) |
申请公布日期 |
2007.12.20 |
申请号 |
US20070846847 |
申请日期 |
2007.08.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPERATION |
发明人 |
JACOBSON HANS M.;KUDVA PRABHAKAR N.;BOSE PRADIP;COOK PETER W.;SCHUSTER STANLEY E. |
分类号 |
G06F1/26;G06F1/32;G06F9/38;G06F9/44 |
主分类号 |
G06F1/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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