| 摘要 |
Disclosed is a verification coverage extraction circuit for extracting the verification coverage rate at the time of circuit verification employing an emulation device, in which a state of the current cycle and a state of the next cycle of a state machine are coupled by a data coupling circuit into an item of data, this data is compressed to a data width which is a necessary minimum to express state transition by an encoder circuit, the state transition information is stored in a memory, with an output of the encoder circuit as an address, and the verification coverage information at the time of functional verification of a circuit under verification is extracted from the memory.
|
