发明名称
摘要 <p>PROBLEM TO BE SOLVED: To minimize the hardware quantity of a data multiplexing circuit which multiplexes and transmits data to be transmitted including variable-length data freely variable in data length by means of specification in advance. SOLUTION: A specified data-length parameter is held in a parameter register 55 and a data-length counter 54 counts up to the count value corresponding to the data length specified by the held data-length parameter. According to this counting operation, a shift register 57 performs shifting operation, and variable-length data included in the transmitted data are outputted sequentially from a multiplexer in response to the shifting operation and multiplexed and transmitted. Consequently, a single data-length counter suffires, thereby making the hardware quantity smaller.</p>
申请公布号 JP4018827(B2) 申请公布日期 2007.12.05
申请号 JP19980355174 申请日期 1998.12.14
申请人 发明人
分类号 H04J3/04;H04J3/16;H04L12/70 主分类号 H04J3/04
代理机构 代理人
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