| 摘要 |
<p>A gate electrode of a MOS transistor and a manufacturing method thereof are provided to reduce a gate length of a high-integrated MOS transistor without reducing a gate electrode length of a mask by forming an edge sidewall of the gate electrode in the form of a recess-etched structure. An isolation layer is formed to divide an active region and an inert region on a semiconductor substrate(100). A gate dielectric(104) and a gate electrode conductive layer are sequentially formed on the semiconductor substrate. The gate electrode conductive layer is dry-etched to form a gate electrode pattern having a preset length on the active region of the semiconductor substrate. The gate electrode pattern is wet-etched to form a gate electrode(106b) whose edge sidewall is recess-etched. The gate dielectric is dry-etched to form a gate dielectric pattern having a preset length. Before the gate electrode pattern is formed, a photoresist pattern(108) defining the gate electrode region having the preset length is formed on the gate electrode conductive layer. After the gate dielectric pattern is formed, the photoresist pattern is removed.</p> |
