FAST TRANSITION FROM LOW-SPEED MODE TO HIGH-SPEED MODE IN HIGH-SPEED INTERFACES
摘要
Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high¬ speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.
申请公布号
WO2007136785(A2)
申请公布日期
2007.11.29
申请号
WO2007US11964
申请日期
2007.05.17
申请人
ATI TECHNOLOGIES, INC.;MACRI, JOSEPH;MOREIN, STEPHEN;LEE, MING-JU, E.;CHEN, LIN
发明人
MACRI, JOSEPH;MOREIN, STEPHEN;LEE, MING-JU, E.;CHEN, LIN