发明名称 |
CIRCUIT FOR CAPTURING FRAME SYNC SIGNAL IN RECEIVER |
摘要 |
<p>I and Q symbol streams are demodulated from a received signal of a wave to be PSK-modulated in which BPSK-modulated frame-synchronizing signal and superframe-identifying signal respectively having a 20-symbol length and an 8PSK-modulated digital signal are time-multiplexed by a demodulating circuit (1). BPSK-demapped bit streams B0 to B3 are generated by a BSPK demapper (3) in accordance with criterion border lines obtained by rotating a basic BPSK criterion border line and a basic criterion border line whose received-signal points are the same as Q-axis on I-Q phase plane by pi /4, 2 pi /4, and 3 pi /4 counterclockwise. When a pattern having a difference of several bits at most from a frame-synchronizing signal is captured from B0 to B3 by first comparing circuits 60 to 63 and thereafter, a pattern having a difference of several bits at most from a superframe-identifying signal is captured by second comparing circuits 64 to 67 after a predetermined certain time, a frame-synchronizing-signal-capturing-signal generating circuit (90) outputs a frame-synchronizing-signal capturing signal (SYN). <IMAGE></p> |
申请公布号 |
EP1039708(B1) |
申请公布日期 |
2007.11.21 |
申请号 |
EP19980959178 |
申请日期 |
1998.12.11 |
申请人 |
KABUSHIKI KAISHA KENWOOD |
发明人 |
SHIRAISHI, KENICHI;HORII, AKIHIRO |
分类号 |
H04L27/22;H04J3/06;H04L7/04 |
主分类号 |
H04L27/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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