发明名称 |
Circuit device with serial test interface and serial test mode procedure |
摘要 |
<p>The arrangement (IC) has a serial test interface (TIF) controlling a test type of operation and a housing (G) accommodating the serial test interface and a processor (CPU). A modulated supply voltage (VDD) is applied to a connecting contact (C1) for transmitting data and/or a clock pulse by making use of two voltage levels (V2, V3). The voltage levels are controlled and are not equal to a feed-in voltage level (V1) for supplying an operating voltage to the arrangement. An independent claim is also included for a serial test operation method for a circuit arrangement.</p> |
申请公布号 |
EP1857827(A2) |
申请公布日期 |
2007.11.21 |
申请号 |
EP20070008192 |
申请日期 |
2007.04.23 |
申请人 |
MICRONAS GMBH |
发明人 |
BIDENBACH, REINER;FRANKE, JOERG;RITTER, JOACHIM;JUNG, CHRISTIAN |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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