| 摘要 |
A method for determining a timing margin to be applied in an integrated circuit timing design. Circuit simulator path delays and static timing analysis tool path delays are determined for the integrated circuit timing design. The circuit simulator path delays are plotted in a first plot versus a percentage difference between the circuit simulator path delays and the static timing analysis tool path delays, and in a second plot are plotted versus a numerical difference between the circuit simulator path delays and the static timing analysis tool path delays. A first point is identified on the second plot having a largest numerical difference, and the circuit simulator path delay for the first point is identified. A corresponding point on the first plot having the circuit simulator path delay is found, and the percentage difference for the corresponding point is identified. A combination of both the circuit simulator path delay and the percentage difference is used as the timing margin.
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