发明名称 |
Data processing device having selective data cache architecture and computer system including the same |
摘要 |
The disclosure is a data processing device with selective data cache architecture and a computer system including the data processing device. The data processing device is comprised of a microprocessor, a coprocessor, a microprocessor data cache, an X-data cache, and a Y-data cache. The microprocessor fetches and executes instructions, and the coprocessor carries out digital signal processing functions. The microprocessor data cache stores data provided from the microprocessor. The X-data cache stores a first group of data provided from the coprocessor while the Y-data cache stores a second group of data provided from the coprocessor.
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申请公布号 |
US7299340(B2) |
申请公布日期 |
2007.11.20 |
申请号 |
US20040774775 |
申请日期 |
2004.02.09 |
申请人 |
SAMSUNG ELECTRONICS., LTD. |
发明人 |
KIM YUN-HWAN;LEE JOONG-EON;LIM KYOUNG-MOOK |
分类号 |
G06F9/28;G06F12/08;G06F9/38;G06F12/00;G06F13/00 |
主分类号 |
G06F9/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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