发明名称 |
Method of fabricating a semiconductor device incorporating a semiconductor constructing body and an interconnecting layer which is connected to a ground layer via a vertical conducting portion |
摘要 |
A semiconductor device includes metal foil to which a ground potential is applied, at a semiconductor constructing body provided on the metal foil and having a semiconductor substrate and a plurality of external connection electrodes provided on the semiconductor substrate. An insulating layer is provided around the semiconductor constructing body and has a thickness substantially equal to the semiconductor constructing body. An one upper interconnecting layer is provided on the semiconductor constructing body and insulating layer, and electrically connected to the external connection electrodes. A vertical conducting portion extends through the insulating layer and electrically connects the metal foil and upper interconnecting layer. |
申请公布号 |
US2007264754(A1) |
申请公布日期 |
2007.11.15 |
申请号 |
US20070880162 |
申请日期 |
2007.07.20 |
申请人 |
CASIO COMPUTER CO., LTD.;CMK CORPORATION |
发明人 |
JOBETTO HIROYASU |
分类号 |
H01L21/56;H01L23/12;H01L21/58;H01L21/60;H01L23/50;H01L23/52;H01L23/538;H01L23/552 |
主分类号 |
H01L21/56 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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