发明名称 COLUMN DECODING ARCHITECTURE FOR FLASH MEMORIES
摘要 An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.
申请公布号 WO2006041790(A3) 申请公布日期 2007.11.15
申请号 WO2005US35528 申请日期 2005.09.30
申请人 ATMEL CORPORATION;SIVERO, STEFANO;BARTOLI, SIMONE;TASSAN CASER, FABIO;RIVA, REGGIORI, RICCARDO 发明人 SIVERO, STEFANO;BARTOLI, SIMONE;TASSAN CASER, FABIO;RIVA, REGGIORI, RICCARDO
分类号 G11C8/00 主分类号 G11C8/00
代理机构 代理人
主权项
地址