Clock jitter calculation device, clock jitter calculation method, and clock jitter calculation program

摘要

In a voltage drop analysis step S 101 , the process calculates a temporal variation of a power source voltage supplied to each cell along a transmission path of a clock signal. In a delay variation rate ratio calculation step S 102 , the process calculates a delay time variation of each cell according to the power source voltage variation. In a clock delay variation amount calculation step S 103 , the process obtains the magnitude of jitter of the clock signal based on the delay time variation.