FERROELECTRIC RANDOM ACCESS MEMORY DEVICE

摘要

A ferroelectric RAM device is provided to decrease remarkably an interval between gates and maintain the size of a pad part same to the conventional method by installing alternately the gate pad part at the both sides of the gate. A ferroelectric RAM device is composed of a DGC structure including MOSFET and MFSFET sharing a floating channel layer. A line shaped channel layer(CH) positioned to a same intervals. A bottom gate(BG) for the MOSFET on which a first pad part(BP) is installed alternately at both side ends of the bottom gate is positioned at a location corresponding to the bottom gate on the channel layer. A top gate(TG) for the MFSFET on which a second pad part(TP) is installed at an inner side of the first pad part is positioned corresponding to the bottom gate.