发明名称 RECONFIGURABLE MULTI-PROCESSING COARSE-GRAIN ARRAY
摘要 A signal processing device adapted for simultaneous processing of at least two process threads in a multi-processing manner is described. It comprises a plurality of functional units capable of executing word- or subword- level operations on data, a means for interconnecting said plurality of functional units, said means for interconnecting supporting a plurality of interconnect arrangements that can be dynamically switched, at least one of said interconnect arrangements interconnecting said plurality of functional units into at least two non- overlapping processing units each with a pre-determined topology, the signal processing device furthermore comprising at least two control modules, each control module being assigned to one of said processing units. The present invention also provides a method for executing an application on such a signal processing device, a method for compilation of application source code in order to obtain compiled code being executable on such a signal processing device, and to optimisation methods for applications to be executed on such a signal processing device.
申请公布号 WO2007106959(A3) 申请公布日期 2007.11.08
申请号 WO2007BE00027 申请日期 2007.03.19
申请人 INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW;FREESCALE SEMICONDUCTORS INC.;KANSTEIN, ANDREAS;BEREKOVIC, MLADEN 发明人 KANSTEIN, ANDREAS;BEREKOVIC, MLADEN
分类号 G06F15/80 主分类号 G06F15/80
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