发明名称 PADDING PROCESSING CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To solve the problem wherein a method for performing padding processing by a padding processing part in an SDRAM interface, when conducting the padding processing as prescribed by H.264 in each MB unit is unsuitable for circuit formation, because the performance of the SDRAM interface is degraded. <P>SOLUTION: Resistors 62-1 to 62-9, formed in an H.264 inter-prediction decoding part, temporarily store reference image data of a minimum block size necessary for the filtering processing of a luminance filter 66. When a moving vector specifies an area, other than an image area of a reference image, image boundary data in an effective image area closest to the area other than the image area are read out from a RAM, and the read image data are temporarily stored in an empty register from among the registers 62-1 to 62-9. The image data, outputted from the register, are padded by a line selector 63, a counter 64 and a shift circuit 65, and the padding-processed image data are outputted in each filtering processing unit of the luminance filter 66. <P>COPYRIGHT: (C)2008,JPO&INPIT</p>
申请公布号 JP2007295215(A) 申请公布日期 2007.11.08
申请号 JP20060120039 申请日期 2006.04.25
申请人 VICTOR CO OF JAPAN LTD 发明人 MATSUMOTO EIJI
分类号 H04N19/50;H03M7/36;H04N19/105;H04N19/117;H04N19/176;H04N19/186;H04N19/20;H04N19/423;H04N19/503;H04N19/51;H04N19/513;H04N19/563;H04N19/80 主分类号 H04N19/50
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