| 发明名称 |
METHOD FOR DESIGNING WIRING STRUCTURE OF LSI |
| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for designing the wiring structure of an LSI in which the wiring capacitance C and the wiring delay RC can be reduced. SOLUTION: The ratio W/T of the wiring width W and the wiring film thickness T of the lower wiring layers of second layer or below is larger than the W/T of the upper wiring layers of third layer or above. COPYRIGHT: (C)2008,JPO&INPIT |
| 申请公布号 |
JP2007288215(A) |
申请公布日期 |
2007.11.01 |
| 申请号 |
JP20070167023 |
申请日期 |
2007.06.25 |
| 申请人 |
TOSHIBA CORP |
发明人 |
SHIGYO NAOYUKI;YAMAGUCHI TETSUYA |
| 分类号 |
H01L21/82;H01L21/3205;H01L21/768;H01L21/822;H01L23/52;H01L23/522;H01L27/04 |
主分类号 |
H01L21/82 |
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