发明名称 SYSTEM FOR CALCULATING REQUIRED AMOUNT OF REDUNDANCY LINE AND FAILURE ANALYSIS METHOD USING THE SAME
摘要 PROBLEM TO BE SOLVED: To provide a technology for easily designing an adequate redundancy line by evaluating the number of required redundancy lines on the basis of a distribution of fail bits being generated in an actually manufactured wafer. SOLUTION: In the system for calculating the required amount of redundancy line, which consists of a database for storing test results of semiconductor memory products and a computer for analyzing the test results, the computer is equipped with a data retrieval function section 111 for retrieving the data from the database and a function section 114 computing the required amount of redundancy lines for obtaining the total number of redundancy lines required for relieving the fail bits on chips to decide redundancy lines to be assigned in respective row/column directions as a breakdown of the number of required redundancy lines and for summing up the total number of redundancy lines required for the relief and the number of redundancy lines assigned to the respective row/column directions. Then the result of process of the function section 114 computing the required amount of the redundancy line is displayed. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007287272(A) 申请公布日期 2007.11.01
申请号 JP20060115234 申请日期 2006.04.19
申请人 HITACHI LTD;ELPIDA MEMORY INC 发明人 ISHIKAWA SEIJI;MORIYAMA ICHIRO
分类号 G11C29/44;G01R31/28;H01L21/82;H01L21/822;H01L27/04 主分类号 G11C29/44
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