发明名称 Data processing apparatus
摘要 The present invention is directed to largely reduce peak current at the time of operation of a boosting circuit provided for an EEPROM. In the erase/write operation, first, a low-frequency clock signal as a selection clock signal is input by a low-frequency clock control signal to a charge pump. After lapse of a certain period (about 1/3 of fall time), a high-frequency clock signal having a frequency higher than that of the low-frequency clock signal is output by a high-frequency clock control signal and is input as the selection clock signal to the charge pump to boost a voltage to a predetermined voltage level. In such a manner, while suppressing the peak of consumption current, the fall time of the boosted voltage can be shortened.
申请公布号 US2007247920(A1) 申请公布日期 2007.10.25
申请号 US20070819288 申请日期 2007.06.26
申请人 KAWAJIRI YOSHIKI;TERASAWA MASAAKI;YAMAZOE TAKANORI 发明人 KAWAJIRI YOSHIKI;TERASAWA MASAAKI;YAMAZOE TAKANORI
分类号 G11C7/00;H01L27/04;G11C5/14;G11C16/12;H01L21/822;H03K5/08 主分类号 G11C7/00
代理机构 代理人
主权项
地址