| 摘要 |
In a method to form a DMOS or bipolar transistor, two epitaxial silicon layers are grown over a silicon substrate instead of the typical one low-resistivity epitaxial layer. The bottom epitaxial layer has a relatively high resistivity of, for example 10 ohms-cm, while the upper epitaxial layer, acting as a drift region, may have a conventional low resistivity such as 3 ohms-cm. The bottom epi layer, being less doped than the upper epi layer, causes a wider and deeper depletion region to occur for a given drain or collector voltage, as compared to a depletion region where the entire epitaxial layer is formed of the upper epitaxial layer composition. Therefore, the parasitic capacitor's depletion region will be wider and deeper when employing the bottom epitaxial layer. The wider and deeper depletion region in the lower epitaxial layer lowers the overall parasitic capacitance value. This improves the switching speed of the transistor. The technique preferably requires no additional process steps so adds no cost to the fabrication process.
|
