| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor and a compiling apparatus, capable of reducing an execution cycle number in parallel processing in a processor which executes a plurality of instructions in one cycle. SOLUTION: Each of registers R0 to R31 is divided into the upper 32-bit area and the lower 32-bit area. A register writing control unit 431 outputs information to the selectors 4321 and 4322 on the registers and the locations (upper and lower areas) in which data are written by the instructions that have issued in one cycle. Each of the selectors 4321 and 4322 selects one out of pieces of data that have been output from first, second and third arithmetic operation units 44, 45 and 46, and writes the selected data in the upper or lower area in one register. COPYRIGHT: (C)2008,JPO&INPIT
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