| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that a drop of a supply voltage occurs in global wiring by the conventional layout method. SOLUTION: In this layout method, a delay adjustment element is inserted in a signal interconnection between basic cells in a semiconductor device wherein the basic cells which each form a functional circuit are arranged for each of a plurality of partial regions divided by power supply interconnections. The delay adjustment elements are arranged based on an amount of delay of a signal between the basic cells arranged for each of the plurality of partial regions to acquire first positional information. Then, based on the first positional information, a total value for power consumption of the delay adjustment elements is calculated for each of the plurality of partial regions. The delay adjustment elements inside first partial regions, out of the plurality of partial regions, which have a total value of power consumption which is a predetermined value or above are relocated to second partial regions, out of the plurality of partial regions, which have a total value of power consumption which is the predetermined value or below. COPYRIGHT: (C)2008,JPO&INPIT
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