发明名称 |
Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions |
摘要 |
A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.
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申请公布号 |
US2007249114(A1) |
申请公布日期 |
2007.10.25 |
申请号 |
US20070820303 |
申请日期 |
2007.06.18 |
申请人 |
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发明人 |
CHEN HUAJIE;CHIDAMBARRAO DURESETI;GLUSCHENKOV OLEG G.;STEEGEN AN L.;YANG HAINING S. |
分类号 |
H01L21/8238 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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