发明名称 Data slicer circuit, demodulation stage, receiving system and method for demodulating shift keying coded signals
摘要 <p>The invention relates to a data slicer (DS) circuit for processing a voltage signal (AF) input having two voltage values (V1, V0), each value representative of a value assigned to one characteristic of a modulated baseband carrier signal (S) corresponding to a binary one or zero bit of information, the data slicer (DS) comprising first means (RD1) for detecting a rising transition segment (RE) of the voltage signal (AF), first means (FD1) for detecting a falling transition segment (FE) of the voltage signal (AF), means (F1) for providing a first serial digital signal output (3) with a binary zero value if a rising transition segment (RE) of the voltage signal (AF) is detected or a binary one value if a falling transition segment (FE) of the voltage signal (AF) is detected or vice versa.</p>
申请公布号 EP1848105(A1) 申请公布日期 2007.10.24
申请号 EP20060300389 申请日期 2006.04.21
申请人 ALCATEL LUCENT 发明人 BRUNSCH, DIETMAR;THOMAS, ALEXANDER
分类号 H03D3/00;H04L27/156 主分类号 H03D3/00
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