发明名称 |
Architectural support for selective use of a high-reliability mode in a computer system |
摘要 |
In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-high-reliability mode of operation. The circuit includes means for causing the circuit to enter the high-reliability mode of operation in response to receiving the second instruction group; means for causing the circuit to enter the non-high-reliability mode of operation in response to receiving the third instruction group; first execution means for executing the first instruction group in the high-reliability mode of operation if the circuit is in the high-reliability mode of operation; and second execution means for executing the first instruction group in the non-high-reliability mode of operation if the circuit is in the non-high-reliability mode of operation.
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申请公布号 |
US7287185(B2) |
申请公布日期 |
2007.10.23 |
申请号 |
US20040819241 |
申请日期 |
2004.04.06 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
SAFFORD KEVIN DAVID;SOLTIS, JR. DONALD CHARLES |
分类号 |
G06F11/00;G06F9/30 |
主分类号 |
G06F11/00 |
代理机构 |
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地址 |
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