| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To eliminate serial position dependency of a threshold voltage characteristic caused by erasing or writing with respect to a volatile memory transistor comprising a NAND type memory array. <P>SOLUTION: In elimination operation, if a gate potential between a source line connection transistor (QS) and a bit line connection transistor (QB) is changed toward a voltage level in a well region by coupling with the well region (PWELL), the gate potential changes a charge storage film of the nonvolatile memory cell at the end of the serial circuit (STRG) to the voltage level similarly in the well region by capacitive coupling. Potential difference between a word line of the nonvolatile memory transistor (QM) located at the end of the serial circuit and the well region is made larger than the potential difference between the word line of the nonvolatile memory transistor located therebetween and the well region. Thus, difference in the potential difference between the well region and the charge storage film is made small between the nonvolatile memory transistors. <P>COPYRIGHT: (C)2008,JPO&INPIT</p> |
