MULTI-LEVEL MEMORY WITH LDPC BIT INTERLEAVED CODED MODULATION

摘要

Embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder (600) to LDPC code data values to be written into the memory cells and an interleaver (602) and a mapper (604) adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values.