发明名称 TEST SYSTEM FOR DIGITAL PROCESSING DEVICE
摘要 PROBLEM TO BE SOLVED: To surely preventing a digital processing device from malfunctioning, even if receiving test-use data at normal mode due to some form of trouble. SOLUTION: A test apparatus 13 is connected to a status signal output terminal that is a normal use output terminal of the digital processing device 11 by using a test jig 14, and the status signal output terminal is forced into its on-state by a test mode switching command generator 13A. A microcomputer 11B from the recognition of the on-state of the status signal output terminal executes a functional test. Test result is transmitted to the test apparatus or a higher-level apparatus 12 through an asynchronous serial data communication. In this transmission, the communication rate in the normal mode is different from that in a test mode, and parity signals in the normal mode and the test mode adopt odd parity in one of the two, and even parity in the other. COPYRIGHT: (C)2008,JPO&INPIT
申请公布号 JP2007271533(A) 申请公布日期 2007.10.18
申请号 JP20060099588 申请日期 2006.03.31
申请人 NIPPON DEMPA KOGYO CO LTD 发明人 SHIOBARA TAKESHI;FURUHATA TSUKASA
分类号 G01R31/28;G01R31/3185 主分类号 G01R31/28
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