发明名称 CYCLIC REDUNDANCY CODE ERROR DETECTION
摘要 A technique to perform carry-less multiplication and bit reflection operations. More specifically, embodiments of the invention include a technique to perform cyclic redundancy code (CRC) generation. A data slice is muliplied by an approximate reciprocial of the generator polynomial and the product is further processed in order to obtain a partial remainder from said data slice. Hence, no modulo operation need to be performed.
申请公布号 WO2006128134(A3) 申请公布日期 2007.10.11
申请号 WO2006US20830 申请日期 2006.05.25
申请人 INTEL CORPORATION;KOUNAVIS, MICHAEL 发明人 KOUNAVIS, MICHAEL
分类号 H03M13/09 主分类号 H03M13/09
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