| 摘要 |
Architecture for transmitting a video signal and an control clock signal between an ASIC and a panel in a display is introduced. Two dummy shift registers (DSRs) and switches are used for sending out the control clock signal to an ASIC. The ASIC compares the control clock signal sent out from the DSR with the video signals desired to be sent to a display panel. Time difference between the control clock signal and the video signals is obtained by the ASIC and the video signals sent out from the ASIC are delayed with the time difference, in order to be synchronized with a shift pulse generated by operation of a shift register in the display.
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