发明名称 Method and device for reduced read latency of non-volatile memory
摘要 Systems, apparatuses and methods for controlling access operations in a memory device that may include a memory controller(s) and memory. Commands, registers and/or other mechanisms may be defined to be supported by the memory device, where such commands, registers, and/or other mechanisms facilitate the control of read and write/erase operations to allow these operations to be performed simultaneously. Thus, a write and/or erase operation may be initiated on a first memory, a read operation initiated by a set of commands on a second memory, wherein the read and write/erase operations are performed substantially at the same time.
申请公布号 US2007239926(A1) 申请公布日期 2007.10.11
申请号 US20060390969 申请日期 2006.03.28
申请人 GYL YEVGEN;HAKKINEN JUSSI;MYLLY KIMMO 发明人 GYL YEVGEN;HAKKINEN JUSSI;MYLLY KIMMO
分类号 G06F12/00 主分类号 G06F12/00
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