| 摘要 |
A method of Digital to Analogue conversion of an input signalDO for suppressing the effect of clock-jitter in a Delta-Sigma analogue to digital converter, or class D amplifier, comprises charging a capacitor (414) to a reference voltage value (Vref) during a first phase ( D i) of a clock signal, discharging the capacitor during a second phase ( D 2) of the clock signal, wherein the discharge is regulated by a biased transistor (418, 419), responsive to the voltage on the capacitor, in a first part of the second phase to provide an approximately constant discharge current, and regulated in a second part of the second phase for rapidly discharging the capacitance means before the end of the second phase; and providing an output (Ud, OUT) as a function of the discharge current and the input signal DO. The output signal Ud, may be applied as a feedback signal to a loop filter in a Delta-Sigma converter Alternatively the output may represent the output of a Class D amplifier. |
