| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a clock generating circuit capable of improving a yield by automatically readjusting the duty of an internal clock to improve an operational speed with respect to an LSI whose operational speed drops because of manufacturing irregularities. <P>SOLUTION: Internal clocks P1. CLK and P2. CLK which respond to the rise and fall of a clock ICLK are inputted to evaluation circuits 13 and 14. The evaluation circuits 13 and 14 compare an expected value with a logical value obtained when a pseudo internal circuit comprising a latch circuit and a logic circuit is synthesized with an internal clock to operate, and output evaluation results. A determination circuit 15 determines a duty at which a target LSI has a maximum operational speed on the basis of the evaluation results. A duty adjustment delay circuit 12 outputs a clock ICLK with which the duty of a reference clock REF. CLK is adjusted on the basis of determination results to a clock driver 2. <P>COPYRIGHT: (C)2004,JPO |
